Renesas Targets Robotics and Industrial Equipment with its New RZ/T2N Quad-Core Chip
Renesas Targets Robotics and Industrial Equipment with its New RZ/T2N Quad-Core Chip
Renesas has announced the RZ/T2N, a new application-class microprocessor designed for robotics and industrial equipment. The chip features a dual-core Arm Cortex-A55 cluster running up to 1,200MHz and a dual-core Cortex-R52 real-time cluster running up to 800MHz. It includes on-board motor control supporting up to four axes, industrial Ethernet with Time-Sensitive Networking (TSN) support, multiple communication interfaces including EtherCAT, PROFINET RT/IRT, and EtherNet/IP, as well as various encoder protocols like Tamagawa T-Format and EnDat 2.2/3. The device also offers error correction code (ECC) memory support, a hardware accelerator for trigonometric functions, and an evaluation board available for $549, though the chips were not yet in sales channels at the time of reporting.
Renesas has launched the RZ/T2N, a quad-core microprocessor integrating four-axis motor control and industrial Ethernet protocols for robotics and industrial automation applications.
Source: Robotics — Web news discovery · Read original article ↗
Article text · Original source · English
Renesas has announced another new entry in its RZ family, this time designed with robotics and industrial equipment firmly in mind: the RZ/T2N, an application-class microprocessor with motor control and industrial Ethernet on-board.
"Industrial equipment designers must balance competing requirements: functionality and performance on one hand, footprint and cost on the other," says Renesas' Hari Pendurty in support of the company's latest launch. "The RZ/T2N solves this challenge by consolidating the essential functions onto a single chip. Combined with our scalable product portfolio, the RZ/T2N gives customers the flexibility to scale their designs for next-generation industrial automation."
Renesas latest RZ chip, the RZ/T2N, packs four-axis motor control and industrial Ethernet support. (📷: Renesas)
The RZ/T2N is built around two processor clusters: a dual-core Arm Cortex-A55 cluster running at up to 1,200MHz plus a dual-core Cortex-R52 real-time cluster running at up to 800MHz. There's 576kB of tightly-coupled memory (TCM) per Cortex-R52 core plus 2MB of on-chip static RAM (SRAM), both with error correction code (ECC) support, with an LPDDR4 interface for external memory. The on-board motor controller offers up to four-axis control, while there's a trio of 12-bit analog to digital converters (ADCs) on board plus a 15-channel delta-sigma intermediate-frequency (IF) interface.
Other features of the chip include an eight-channel motor encoder interface supporting two channels per axis in Tamagawa T-Format, HIPERFACE DSL, A-format, EnDat 2.2, BiSS C, EnDat 3, BiSS Line protocols, a trio of gigabit Ethernet MACs with Time-Sensitive Networking (TSN) support, on-board Ethernet switch, and an EtherCAT Sub-Device Controller (ESC) for industrial Ethernet connectivity, PROFINET RT/IRT and EtherNet/IP support, four SPI, three I2C, 14 SCI, and two CAN-FD buses, on-board security block with true random number generator (TRNG), and a hardware accelerator for trigonometric functions.
More information on the RZ/T2N is available on the Renesas website; an evaluation board is available to order at $549, but the chips themselves had not yet appeared in the sales channel at the time of writing.
What the source reports
Publisher-reported claims, with original evidence. These results have not been independently verified by RoboSignal.
Reported numbers
evaluation board cost
549
View original evidence
ailable to order at $549, but the chips themselves had not yet appeared in the sales channel at the time of writing.
Open source S7processor frequency (Cortex-A55)
≤1,200
View original evidence
two processor clusters: a dual-core Arm Cortex-A55 cluster running at up to 1,200MHz plus a dual-core Cortex-R52 real-time cluster running at up to 800MHz. There's 576kB of tightly-coupled memory (TCM) per Cortex-R52 core plus 2MB of on-chip static RAM (SRAM), both with error correction code (ECC) support, with an LPDDR4 interface for external memory. The on-board motor controller offers up to four-axis control, whil
Open source S4processor frequency (Cortex-R52)
≤800
View original evidence
two processor clusters: a dual-core Arm Cortex-A55 cluster running at up to 1,200MHz plus a dual-core Cortex-R52 real-time cluster running at up to 800MHz. There's 576kB of tightly-coupled memory (TCM) per Cortex-R52 core plus 2MB of on-chip static RAM (SRAM), both with error correction code (ECC) support, with an LPDDR4 interface for external memory. The on-board motor controller offers up to four-axis control, whil
Open source S4TCM per Cortex-R52 core
576
View original evidence
two processor clusters: a dual-core Arm Cortex-A55 cluster running at up to 1,200MHz plus a dual-core Cortex-R52 real-time cluster running at up to 800MHz. There's 576kB of tightly-coupled memory (TCM) per Cortex-R52 core plus 2MB of on-chip static RAM (SRAM), both with error correction code (ECC) support, with an LPDDR4 interface for external memory. The on-board motor controller offers up to four-axis control, whil
Open source S4on-chip SRAM
2
View original evidence
two processor clusters: a dual-core Arm Cortex-A55 cluster running at up to 1,200MHz plus a dual-core Cortex-R52 real-time cluster running at up to 800MHz. There's 576kB of tightly-coupled memory (TCM) per Cortex-R52 core plus 2MB of on-chip static RAM (SRAM), both with error correction code (ECC) support, with an LPDDR4 interface for external memory. The on-board motor controller offers up to four-axis control, whil
Open source S4motor control axes
4
View original evidence
the company's latest launch. "The RZ/T2N solves this challenge by consolidating the essential functions onto a single chip. Combined with our scalable product portfolio, the RZ/T2N gives customers the flexibility to scale their designs for next-generation industrial automation." Renesas latest RZ chip, the RZ/T2N, packs four-axis motor control and industrial Ethernet support. (📷: Renesas) The RZ/T2N is built around
Open source S3ADC channels
3
View original evidence
e there's a trio of 12-bit analog to digital converters (ADCs) on board plus a 15-channel delta-sigma intermediate-frequency (IF) interface. Other features of the chip include an eight-channel motor encoder interface supporting two channels per axis in Tamagawa T-Format, HIPERFACE DSL, A-format, EnDat 2.2, BiSS C, EnDat 3, BiSS Line protocols, a trio of gigabit Ethernet MACs with Time-Sensitive Networking (TSN) suppo
Open source S5
- paper: not_reported
- code: not_reported
- weights: not_reported
- dataset: not_reported
Source excerpts and review record
Automatically extracted; no manual editorial approval recorded.
ailable to order at $549, but the chips themselves had not yet appeared in the sales channel at the time of writing.
Open source S7
two processor clusters: a dual-core Arm Cortex-A55 cluster running at up to 1,200MHz plus a dual-core Cortex-R52 real-time cluster running at up to 800MHz. There's 576kB of tightly-coupled memory (TCM) per Cortex-R52 core plus 2MB of on-chip static RAM (SRAM), both with error correction code (ECC) support, with an LPDDR4 interface for external memory. The on-board motor controller offers up to four-axis control, whil
Open source S4
the company's latest launch. "The RZ/T2N solves this challenge by consolidating the essential functions onto a single chip. Combined with our scalable product portfolio, the RZ/T2N gives customers the flexibility to scale their designs for next-generation industrial automation." Renesas latest RZ chip, the RZ/T2N, packs four-axis motor control and industrial Ethernet support. (📷: Renesas) The RZ/T2N is built around
Open source S3
e there's a trio of 12-bit analog to digital converters (ADCs) on board plus a 15-channel delta-sigma intermediate-frequency (IF) interface. Other features of the chip include an eight-channel motor encoder interface supporting two channels per axis in Tamagawa T-Format, HIPERFACE DSL, A-format, EnDat 2.2, BiSS C, EnDat 3, BiSS Line protocols, a trio of gigabit Ethernet MACs with Time-Sensitive Networking (TSN) suppo
Open source S5
rt, on-board Ethernet switch, and an EtherCAT Sub-Device Controller (ESC) for industrial Ethernet connectivity, PROFINET RT/IRT and EtherNet/IP support, four SPI, three I2C, 14 SCI, and two CAN-FD buses, on-board security block with true random number generator (TRNG), and a hardware accelerator for trigonometric functions. More information on the RZ/T2N is available on the Renesas website ; an evaluation board is av
Open source S6
Source：Robotics — Web news discovery · hackster.io