The World Model Planning Accelerator (WMPA): Hardware-Algorithm Co-Design for Embedded AI in Robotics
The World Model Planning Accelerator (WMPA): Hardware-Algorithm Co-Design for Embedded AI in Robotics
This paper introduces the World Model Planning Accelerator (WMPA), a chip architecture designed for embedded robotics to run world models efficiently. The authors analyze the energy and thermal bottlenecks of current GPU-based recurrent state space models, deriving theoretical lower bounds on computation and dynamic energy. They show that existing implementations are memory-bandwidth bound and generate excessive heat, reaching 556 K in simulations. To address this, WMPA integrates near-memory computation, variable-precision units, and copy-on-write scratchpads to target a 40x reduction in power consumption, keeping silicon tiles near ambient temperatures (306 K) in simulation, aiming to enable practical planning on thermally constrained robots.
The authors derive theoretical lower bounds on energy for world model inference and demonstrate that current GPU implementations are memory-bandwidth bound and thermally inefficient, proposing a new chip architecture (WMPA) designed to reduce power consumption by targeting 40x improvement while maintaining ambient operating temperatures in simulation.
Source: arXiv Robotics — research abstracts · Read original article ↗
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What the source reports
Publisher-reported claims, with original evidence. These results have not been independently verified by RoboSignal.
Reported numbers
energy consumption
5.9
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hardware sits from it, have not been characterized. We derive lower bounds on the arithmetic operations and the CMOS dynamic energy of a latent state transition from information theory and Boolean circuit complexity. Profiling a DreamerV3-style Recurrent State Space Model (RSSM) shows that every rollout operation is memory-bandwidth bound and that a GPU consumes at least $5.9\times10^{10}$ times the CMOS energy floor
Open source S3power reduction target
40
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entropy estimation, variable-precision rollout units, and copy-on-write latent scratchpads. With a design target of 40x lower power, the same tile stays near ambient at 306 K in simulation, pointing toward practical planning on thermally constrained robots.
Open source S5
- paper: not_reported
Source excerpts and review record
Automatically extracted; no manual editorial approval recorded.
hardware sits from it, have not been characterized. We derive lower bounds on the arithmetic operations and the CMOS dynamic energy of a latent state transition from information theory and Boolean circuit complexity. Profiling a DreamerV3-style Recurrent State Space Model (RSSM) shows that every rollout operation is memory-bandwidth bound and that a GPU consumes at least $5.9\times10^{10}$ times the CMOS energy floor
Open source S3
. Transient 3D thermal simulations show that this inefficiency is also a thermal one, since sustained back-to-back planning heats a millimeter-scale silicon tile to 556 K even behind an ideal copper heat spreader. Guided by this chain from bound to bottleneck, we propose the World Model Planning Accelerator (WMPA), a chip architecture for embedded world model planning that combines near-memory computation, real-time
Open source S4
entropy estimation, variable-precision rollout units, and copy-on-write latent scratchpads. With a design target of 40x lower power, the same tile stays near ambient at 306 K in simulation, pointing toward practical planning on thermally constrained robots.
Open source S5
Source：arXiv Robotics — research abstracts · arxiv.org