Planners Exploit Deterministic Error: Dithered Low-Bit World Models
Overview
This research abstract introduces a technique where sampling-based planners exploit deterministic errors introduced by round-to-nearest activation quantization. By applying shared dither redrawn at every iteration, the authors demonstrate that planning collapse can be significantly reduced in low-bit world models (e.g., W8A4 integer) without calibration or training. The study reports speedups of 1.9-3.3x for planning rollouts and 1.3-1.5x for whole planning steps on an Ampere GPU compared to FP32, alongside improved success rates in affected tasks within the TD-MPC2 benchmark suite.
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Event evidence and corrections
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Reported quantity · success points lost: 100 other · Basis not reported
“arXiv:2611.11780v1 Announce Type: new Abstract: Sampling-based planners such as MPPI and CEM query a learned world model thousands of times per control step, so low-bit world models are an obvious way to make model-based control cheaper on a robot. With round-to-nearest activation quantization and no calibration, we find that planning can collapse, by up to 100 points of success, while the world model's latent one-st”
Exact source · revision 1Source owner not reported
Reported quantity · planning speedup factor: 1.9 other · Basis not reported
“on an Ampere GPU, a W8A4 integer TD-MPC2 world model runs its planning rollouts 1.9-3.3$\times$ and the whole planning step 1.3-1.5$\times$ faster than FP32, though not faster than BF16 with pre-converted weights; shared dither adds at most 2.3% latency. In TD-MPC2, block-scaled NVFP4 removes most of the damage and MXFP4 part of it, which ties the failure to coarse grids with a shared scale. Hypotheses, thresholds a”
Exact source · revision 1Source owner not reported
Reported quantity · planning step speedup factor: 1.3 other · Basis not reported
“on an Ampere GPU, a W8A4 integer TD-MPC2 world model runs its planning rollouts 1.9-3.3$\times$ and the whole planning step 1.3-1.5$\times$ faster than FP32, though not faster than BF16 with pre-converted weights; shared dither adds at most 2.3% latency. In TD-MPC2, block-scaled NVFP4 removes most of the damage and MXFP4 part of it, which ties the failure to coarse grids with a shared scale. Hypotheses, thresholds a”
Exact source · revision 1Source owner not reported
Reported quantity · parameter count: 317000000 other · Basis not reported
“ither fixed within a step or an episode brings the drift back. Dither shared by all candidates and redrawn at every iteration removes most of the damage at the same bit width and without training: at least half of it in all 19 affected Meta-World cells (task $\times$ bit width) of TD-MPC2 (median 95%), in 4 of 5 DINO-WM cells, and in all 8 affected tasks of a 317M-parameter multi-task TD-MPC2. Captured as CUDA graphs”
Exact source · revision 1Source owner not reported
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- arXiv Robotics — research abstractsSignalPlanners Exploit Deterministic Error: Dithered Low-Bit World Models
This research abstract introduces a technique where sampling-based planners exploit deterministic errors introduced by round-to-nearest activation quantization. By applying shared dither redrawn at every iteration, the authors demonstrate that planning collapse can be significantly reduced in low-bit world models (e.g., W8A4 integer) without calibration or training. The study reports speedups of 1.9-3.3x for planning rollouts and 1.3-1.5x for whole planning steps on an Ampere GPU compared to FP32, alongside improved success rates in affected tasks within the TD-MPC2 benchmark suite.
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